The present invention relates to semiconductor manufacturing technology, and more particularly to a source-drain structure and method of manufacturing the same.
It is generally known in the art, when programming an individual memory cell within a bit line, all of the memory cells sharing the same bit line are subject to a high drain bias, which is referred to as drain disturb or program disturb. Meanwhile, continuing drain bias leading to a long pulse time of a read operation will cause a soft-write operation of the memory cells sharing the same bit line. As the size of flash memory devices continues to shrink, the drain bias leading to drain disturbance in the bit lines of a flash memory array limits the reliability of a flash memory device.
Referring to FIG. 1, during the programming operation, although a memory cell A does not detect a gate voltage, the memory cell A can detect the programming drain voltage (about 4 V). This stress voltage is present when any of the memory cells of a bit line (there may be thousands of memory cells) is being programmed. The high floating gate potential on the erased cell facilitates electron injection into the floating gate, if the tunnel oxide quality is poor, a programmed cell can lose charge due to the high electric field between the drain and the floating gate. Thus, it is important to ensure a good quality of tunnel oxide even after several programming and erase cycles.
Particularly, for a typical memory device unit, a certain drain voltage is required by a channel hot electron (CHE) program mechanism, the channel doping level must be very high to prevent cell punch-through from occurring under the high programming voltage. The high channel doping level results in a relatively steep doping distribution at the drain junction, that generates a tunneling effect, to thereby stimulate hot electron effect, so that a high electric field is generated in the traverse direction of the drain-substrate junction, which increases the drain disturbance and reduces the device reliability. Therefore, reducing the maximal electric field in the drain-substrate junction of flash memory cells, and hence reducing the generation of hot carriers is a key approach to suppress drain and read disturbs.
FIGS. 2A through 2C are cross-sectional views of intermediate stages of a conventional method of manufacturing a source-drain structure. FIG. 2A is a cross-sectional view of a semiconductor structure after the formation of a first gate electrode, a second gate electrode, and a third electrode. Referring to FIG. 2A, a source region 10′ is formed in a portion located between a first gate electrode a1′ and a second gate electrode a2′, a drain region 20′ is formed in a portion located between the second gate electrode a2′ and a third gate electrode a3′. Thereafter, an opposite-conductivity type ion implantation (i.e., an ion implantation with the opposite conductivity type) is performed into a self-aligned source region 102′ by controlling the implantation angle, dose and energy to form a source-substrate junction 103′ in the side surface and bottom side of the self-aligned source region 102′.
FIG. 2B is a cross-sectional view of an intermediate stage after the formation of a lightly doped drain region by performing a lightly doped drain implant. The lightly doped drain junction 104′ has an edge curvature that is relatively small with respect to the edge curvature of the source-substrate junction 103′, so that the edge of the lightly doped drain junction 104′ is relatively steep with respect to the source-substrate junction 103′.
FIG. 2C is a cross-sectional view illustrating the stage after spacers have been formed on sidewalls of the first, second, and third gate electrodes. The spacers between the first and second gate electrodes a1′, a2′ are in physical contact. Then, an ion implantation is performed into the exposed portion of the substrate 101′ located between the second and third gate electrodes a2′ and a3′ to form a heavily doped drain region 107′.
The prior art approach typically utilizes a low operating voltage to suppress the drain disturb, so that the device performance is improved at the expense of reduced programming speed. Therefore, a novel method is needed to solve the problems of drain disturb present in the source-drain structure.